The present invention relates in general to semiconductor structures and methods for forming the same, and more particularly to semiconductor power field effect transistors (FETs) with low resistance channel regions.
Some conventional vertically conducting trench-gate power MOSFETs include an n-type substrate over which an n-type epitaxial layer extends. The substrate embodies the drain of MOSFET. A p-type body region extends into the epitaxial layer. Trenches extend through the body region and into the portion of the epitaxial layer bounded by the body region and the substrate (commonly referred to as the drift region). A dielectric layer lines the sidewalls and bottom of each trench. Gate electrodes (e.g., from polysilicon) are formed in the trenches and embody the gate of the MOSFET. Source regions extend into the body regions and flank the trenches. Heavy body regions are formed in the body regions between the source regions. When the MOSFET is in the on state, a current flows vertically through the channel region formed in the body region between the source regions and the drift region along the trench sidewalls.
To obtain high current capability, the transistor on-resistance needs to be reduced. One contributing factor to the on-resistance is the channel resistance. Also, minimizing the resistance of the body region helps improve the UIS (unclamped inductive switching) capability of the transistor. Various techniques for reducing the channel resistance and/or the resistance of the body region have been proposed but with limited success. Thus, there is a need for techniques which enable significant reduction in the channel resistance and the resistance of the body region for n-channel and p-channel power transistors.